During the semiconductor manufacturing process, a wafer is fabricated one layer after another. In each layer, geometric patterns associated with circuit components are printed in photoresists by photolithography, which are followed by etching and film deposition to create patterns of various materials such as metal, semiconductor and insulator. Defective wafers sometimes occur in the process, especially when the yield is being ramped up. In general, few remedy methods exist for a defective wafer. However, wafers with defective photoresist patterns can be reworked to reduce manufacturing costs. Rework involves a plasma and/or chemical solvent removal of the photoresist film.
Defective photoresist patterns typically have critical dimension errors and/or overlay errors. Critical dimension errors are errors involving feature sizes, while overlay errors are errors associated with how two patterning layers such as a via and a metal line overlap. Conventionally, specifications for critical dimension errors and overlay errors are established based on layout design rules, device performance and reliability requirements. These specifications usually do not consider either manufacturing condition variations (e.g., dose, focus and alignment) between lots or batches or differences between circuit designs. At the advanced technology nodes with increasing proximity effects between neighboring features, these factors can cause defective wafers and significantly lower the yield. Conventionally, worst-case critical dimension/overlay error tolerances are often used for determining the specifications. This increases rework rates, expands unnecessary manufacturing resources, extends fabrication time and results in increased manufacturing costs.
Accordingly, there is a need for methods of wafer rework determination that are based on particular circuit designs and utilize in-fab metrology data. The presently disclosed technology attempts to meet this need.